1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to a structure for reading data from a memory cell of a static semiconductor memory device.
2. Description of the Background Art
FIG. 22 schematically shows a structure of an array portion of a conventional static semiconductor memory device. FIG. 22 shows the structure of the array portion of a static random access memory (SRAM) which is one of the static semiconductor memory devices. In FIG. 22, the SRAM includes a plurality of memory cells M arranged in rows and columns, word lines WL arranged corresponding to respective rows of memory cells and having memory cells of the corresponding rows connected, and a plurality of bit line pairs BL, /BL arranged corresponding to respective columns of the memory cells and having memory cells of the corresponding column connected. FIG. 22 shows, as representatives, one word line WL1, bit line pairs BL1, /BL1 to BLn, /BLn, and memory cells M1 to Mn arranged corresponding to crossing points of these lines.
Each of the memory cells M1 to Mn includes an inverter latch formed by inverters 202 and 203 for storing information at storage nodes SN and /SN, and access transistors 204 and 205 which are rendered conductive in response to a signal potential on word line WL1 for connecting storage nodes SN and /SN to bit lines BL, /BL (BL1, /BL1 to BLn, /BLn), respectively. Access transistors 204 and 205 are formed of n channel MOS transistors (insulated gate type field effect transistors).
SRAM further includes bit line precharge/equalize circuits BEQ1 to BEQn provided corresponding to bit line pairs BLI, /BL1 to BLn, /BLn, respectively, and activated when a bit line equalize instructing signal /EQ is activated, for precharging and equalizing corresponding bit lines BL1, /BL1 to BLn, /BLn to the level of power supply voltage Vcc; column selection gates CSG1 to CSGn receiving a column selection signal Y (Y1 to Yn) from a column decoder, not shown, rendered conductive when the received column selection signal Y designates the corresponding bit line pair, for electrically connecting the corresponding bit line pairs BL1, /BL1 to BLn, /BLn to internal read data bus DB, /DB; and a sense amplifier 215 which is activated at the time of data reading, for amplifying signal potential on the internal read data buses DB, /DB, generating and transmitting to an output buffer circuit, not shown, an internal read data.
Each of the bit line precharge/equalize circuits BEQ1 to BEQn includes a p channel MOS transistor 206 which is rendered conductive when the bit line equalize instructing signal /EQ is activated, to transmit power supply voltage Vcc to the bit line BL (BL1 to BLn), a p channel MOS transistor 207 which is rendered conductive when the bit line equalize instructing signal /EQ is activated, to transmit power supply voltage Vcc to the bit line /BL (/BL1 to /BLn), and a p channel MOS transistor 208 which is rendered conductive when the bit line equalize instructing signal /EQ is activated, to electrically connect bit lines BL and /BL.
Each of the column selection gates CSG1 to CSGn includes an inverter circuit 210 for inverting the column selection signal Y (Y1 to Yn), a transmission gate 211 which is rendered conductive in accordance with the column selection signal Y and an output signal from inverter circuit 210, to connect the corresponding bit line BL (BL1 to BLn) to the internal read data bus DB, and a transmission gate 212 which is rendered conductive in accordance with the column selection signal Y and the output signal from inverter 210, to connect the corresponding bit line /BL (/BL1 to /BLn) to the internal read data bus /DB.
Sense amplifier 215 has a structure of a differential amplifier circuit such as shown, for example, in Japanese Patent Laying-Open No. 7-226083. The operation of the SRAM shown in FIG. 22 at the time of data reading will be described with reference to the diagram of signal waveforms of FIG. 23.
In data reading, bit line equalize instructing signal /EQ is driven to the inactive state of H level. In data writing, bit line equalize instructing signal /EQ is set to be and kept inactive for a prescribed time period, so that the bit line fully swings between the levels of the power supply voltage and the ground voltage in accordance with the write data. In data reading, bit line equalize/precharge circuits BEQ1 to BEQn have a function of making smaller the amplitude of the bit line potential and reading data at high speed.
When an address signal is applied, a row decoder and a column decoder, not shown, operate in accordance with the applied address signal, and the word line corresponding to the addressed row and the column selection signal corresponding to the addressed column are driven to the selected state. FIG. 23 shows an example in which word line WL1 is selected. In response to the rise of the potential on word line WL1, access transistors 204 and 205 of memory cells Ml to Mn connected to the word line WL1 are rendered conductive, and respective storage nodes SN and /SN are connected to the corresponding bit lines BL, /BL (BL1, /BL1 to BLn, /BLn). Bit line precharge/equalize circuits BEQ1 to BEQn are activated when the memory cell is not selected, and inactivated when the memory cell is selected. In accordance with the column selection signal Y, the bit lines corresponding to the selected column are connected to the internal read data bus DB, /DB. One of the storage nodes SN and /SN is at the H level and the other is at the L level.
Now, assume that memory cell Ml is selected and storage node SN stores data at the H level. In this state, a current (column current) flows from bit line /BL1 to storage node /SN, and the voltage level of bit line /BL1 lowers. Meanwhile, storage node SN stores the H level data, and the voltage level of bit line BL1 hardly changes. MOS transistor 208 in bit line precharge/equalize circuit BEQ1 prevents the potential difference between bit lines BL1 and /BL1 from becoming too large. The potential difference developed between bit lines BL1 and /BL1 is transmitted to internal read data bus DB and /DB through column selection gate CSG1. Sense amplifier 215 is activated at a prescribed timing, so that it amplifies the potential difference between internal read data bus DB and /DB and generates internal read data.
When reading of the memory cell data is completed, the selected word line WL1 attains to the inactive state of L level, and the column selection signal Y1 falls to the inactive state of L level. Consequently, bit lines BL1 and /BL1 are disconnected from internal read data bus DB and /DB, and bit lines BL1, /BL1 to BLn, /BLn are again precharged to the original level of the power supply voltage Vcc by corresponding bit line precharge/equalize circuits BEQ1 to BEQn.
FIG. 24 shows an example of a specific structure of the memory cells M1 to Mn shown in FIG. 22. In FIG. 24, reference character M generally represents a memory cell. In FIG. 24, memory cell M includes a resistance element 220 having high resistance connected between a power supply node and storage node /SN; a driver transistor 221 consisting of an n channel MOS transistor connected between storage node /SN and the ground node and having a gate connected to the storage node SN; a resistance element 222 having high resistance connected between the power supply node and storage node SN; a driver transistor 223 consisting of an n channel MOS transistor connected between storage node SN and the ground node and having a gate connected to storage node /SN; and access transistor 204 consisting of an n channel MOS transistor for connecting storage node SN to the bit line BL in response to the signal potential on the word line WL; and an access transistor 205 consisting of an n channel MOS transistor for connecting storage node /SN to the bit line /BL in response to the signal potential on word line WL. Resistance element 220 having high resistance and driver transistor 221 correspond to inverter 202 of the memory cell shown in FIG. 22, and resistance element 222 having high resistance and driver transistor 223 correspond to inverter 203 of the memory cell shown in FIG. 22.
When data at the H level is stored in storage node SN, driver transistor 221 is conductive, and storage node /SN is held at the level of the ground voltage. In this state, driver transistor 223 is non-conductive, and storage nodes SN and /SN are held at the H level and L level, respectively.
When resistance elements 220 and 222 are formed, for example, of polysilicon resistance, it is possible to form these resistance elements 220 and 222 having high resistance above driver transistors 221 and 223, and therefore it becomes possible to reduce an area occupied by the memory cells. The resistance value of these resistance elements having high resistance is sufficiently higher than ON resistance (channel resistance) of access transistors 204 and 205 as well as driver transistors 221 and 223. In order to surely hold the data stored in storage nodes SN and /SN when the word line WL is set to the selected state and access transistors 204 and 205 are rendered conductive, it is necessary that transfer factor .beta.a (ratio of channel width Wa to channel length La) of access transistors 204 and 205 is set as large as at least three times the transfer factor .beta.b of driver transistors 221 and 223. The necessity of making different the transfer factor .beta. of access transistors and driver transistors will be described in the following.
FIG. 25A shows an inverter I, and FIG. 25B shows input/output transfer characteristics of inverter I. Inverter I inverts an input signal IN to produce an output signal OUT. The larger the gain of inverter I, the steeper the change in the curve representing input/output transfer characteristic shown in FIG. 25B. The gain of inverter I is determined by current drivability of the MOS transistors constituting the inverter.
FIG. 26A shows a structure of an inverter latch. The inverter latch is used in the SRAM cell shown in FIGS. 22 and 24. More specifically, inverter 202 inverts the signal potential on storage node SN for transmission to storage node /SN, while inverter 203 inverts the signal potential on storage node /SN for transmission it to storage node SN.
In FIG. 26B, curve A1 represents input/output transfer characteristic of inverter 202, while a curve A2 represents input/output transfer characteristic of inverter 203. When inverters 202 and 203 have the same input/output transfer characteristic, curve A2 is obtained by folding curve A1 along the dotted line shown in FIG. 26B. Crossing points S1 and S2 of curves Al and A2 are stable points of this inverter latch. A voltage corresponding to one of the states at stable points S1 and S2 appears at storage nodes SN and /SN.
For stable operation of the inverter latch, the curves shown in FIG. 26B must have two stable points S1 and S2. A point PM is a meta stable point. Even when nodes SN and /SN in the initial state are at potentials corresponding to a state near point PM, a certain noise shifts the latch state to stable point S1 or S2. In order to implement such a state that the inverter latch formed of inverters 202 and 203 stably operate as a flipflop to hold stably the potentials of storage nodes SN and /SN, a portion surrounded by curves A1 and A2 (defined as a static noise margin SNM) must be large. If this portion were small, curves A1 and A2 would be close to each other, and any point in such close portion would function as a false stable point, possibly causing a signal potential of at an arbitrary stable point to appear at storage nodes SN and /SN.
FIG. 27A shows a standby state (word line non-selected state) of a static memory cell. In FIG. 27A, access transistors 204 and 205 are non-conductive. In this state, storage nodes SN and /SN are connected to power supply nodes via high resistance elements 222 and 220. Resistance element 220 and driver transistor 221 constitute inverter 202, and resistance element 222 and driver transistor 223 constitute inverter 203. In the inverter employing the high resistance elements, the output node is rapidly discharged when the driver transistor is rendered conductive (current supplying capability of high resistance element is extremely small). Therefore, in this case, input/output transfer characteristic of the inverter latch has extremely steep transition portion allowing stable holding of data, as shown in FIG. 27B.
FIG. 28A shows a state of the static memory cell when the word line is in the selected state. In this state, access transistors 204 and 205 are rendered conductive, and storage nodes SN and /SN are connected to the corresponding bit lines BL and /BL, respectively. A current flows from the corresponding bit line to that one of the storage nodes SN and /SN which holds the potential of L level. This state is equivalent to a structure in which a load of low impedance is connected in parallel to the high resistance element, and therefore, equivalent to a structure in which high resistance elements 220 and 222 are not present. Therefore, in this state, inverters 202 and 203 must be treated as NMOS enhancement type load inverters using access transistors 204 and 205 as loads. In this case, a current is supplied from the NMOS enhancement type load transistor, the change at the transition portion of the input/output transfer characteristic is more moderate and the gain is lower, as compared with the case where high resistance element is used. Accordingly, the area surrounded by the curves A1 and A2 becomes smaller and, the static noise margin becomes smaller, as shown in FIG. 28B.
Assume that access transistors 204 and 205 and driver transistors 221 and 223 have the same current drivability. In this state, the amount of current discharged by the driver transistor which is conductive (for example, transistor 223) is the same as the amount of current supplied by the access transistor (for example, transistor 204), the input/output transfer characteristic of inverters 202 and 203 is extremely moderate, and curves A1 and A2 nearly attain such a state that only one stable point is present, as shown in FIG. 28C. More specifically, when the access transistor and the driver transistor have the same current drivability, the access transistor and the driver transistor holding data of L level come to have the same conductance when the word line is selected. Therefore, the potential of the storage node holding the L level data rises, the other driver transistor holding the H level data is rendered conductive, and the potential of the storage node storing the H level data is lowered.
Stable points S1 and S2 are operation points of the flipflop constituted by the inverters, and the flipflop is held in either one of these states. Accordingly, when input/output transfer characteristic changes as shown in FIG. 28C, bistable point disappears (only a monostable point is present), and the data held in storage nodes SN and /SN are destroyed when the word line is selected. Therefore, in order to ensure two stable points in the input/output transfer characteristic of the inverter latch, it is necessary to prevent the potentials of storage nodes SN and /SN from shifting to the intermediate potential level. In other words, it is necessary to make smaller the ratio between conductances of access transistor and driver transistor. Namely, it is necessary to set current drivability (conductance) of the driver transistor larger than the current drivability (conductance) of the access transistor.
The current drivability (conductance) of the MOS transistor is in proportion to the ratio (transfer factor) .beta. of channel width W to channel length L. The ratio (cell ratio) R of current drivability is set to a value between 3 to 4, as already described. Consequently, input/output transfer characteristics of the inverter is made relatively steep, so that two stable points are ensured and destruction of stored data at the time of data reading can be prevented.
In order to set transfer factor .beta. of driver transistors 221 and 223 larger than that of access transistors 204 and 205, it is necessary to set channel widths of driver transistors 221 and 223 wider than those of access transistors 204 and 205. If channel length only is reduced, the short-channel effect occurs, so that the threshold voltage lowers and current consumption increases. Therefore, in order to hold data stably in the data read operation, driver transistors 221 and 223, must have sizes (ratios of channel width to channel length) larger than those of the access transistors. Accordingly, memory cell size (area of occupation) cannot be made small, which hinders higher integration.
Meanwhile, operational power supply voltage is made lower and lower to realize higher speed of operation and lower current consumption. In an MOS transistor, the higher the gate voltage, the larger drain current can be supplied. This is understood from the fact that drain current in the saturation region of the MOS transistor is represented by the following equation EQU Ids=.beta.(Vgs-Vth).sup.2
where Vgs represents gate-to-source voltage, and Vth represents a threshold voltage. Therefore, when the power supply voltage becomes lower, the gate-to-source voltage Vgs is reduced, and the amount of driven current decreases. As a result, transition of the input/output transfer characteristic of the inverter becomes slower, resulting in such input/output transfer characteristic as shown in FIG. 28C, possibly causing destruction of the stored data at the time of data reading.
Specially in this memory cell, current is always supplied through the resistance elements, and in order to reduce current consumption as much as possible, the threshold voltage of driver transistors 221 and 223 is made higher than that of the access transistor. Therefore, when the power supply voltage is made lower, difference between current drivability of conductive driver transistors 221 and 223 and current drivability of conductive access transistors 204 and 205 becomes smaller. Therefore, the change in the transition portion of curves A1 and A2 becomes extremely moderate as shown in FIG. 28D, resulting in a state in which there is not a stable point but only a quasi stable point. Accordingly, the stored data is destroyed when the word line is selected, and data cannot be read. Stable data holding is not ensured.
Further, column current flows from the bit line precharge/equalize circuit BEQ to the memory cell at the time of data reading, resulting in considerable current consumption.